There are numerous types of non-volatile memories, i.e. memories retaining information stored in the absence of electrical supply, able to be written and/or erased electrically:                EPROMs (<<Erasable Programmable Read Only Memories>>), the contents whereof can be written electrically, but which have to be subjected to UV radiation in order to erase the stored information;        EEPROMs (<<Electrically Erasable Programmable ROMs>>), the contents whereof can be written and erased electrically, but which require for their production larger semiconductor surfaces than memories of the EPROM type, and which are therefore more costly to produce.        
There are also non-volatile memories, called Flash memories, which do not have the drawbacks of the aforementioned EPROM or EEPROM memories. A Flash memory is formed by a plurality of memory cells capable of being electrically programmed individually, a large number of cells, called a block, sector or page, capable of being erased simultaneously and electrically. Flash memories combine both the advantage of EPROM memories in terms of integration density and the advantage of EEPROM memories in terms of the electrical erasure.
Moreover, the durability and the reliable electrical consumption of Flash memories make them advantageous for numerous applications: digital cameras, cell phones, printers, personal organisers, laptop computers, or portable reader and sound recording devices, USB sticks, etc. Moreover, Flash memories do not have mechanical elements, which endow them with a fairly considerable resistance to impacts.
The majority of Flash memories are of the <<stand-alone>> type and have large storage capacities, generally greater than 1 Gb, and are dedicated to mass storage applications.
However, there are also so-called embedded Flash memories (<<embedded memories>>), the production of which is integrated into a CMOS type process and which are becoming of increasing interest, for example in the areas of the car and microcontrollers, for the storage of data or codes. These embedded Flash memories are produced on a chip which also comprises CMOS devices intended to perform logic functions other than the storage of data. These embedded Flash memories are generally produced for smaller storage capacities than those of <<stand-alone>> type memories, their capacities being able to vary generally from several bits to several Mb. The features of the embedded Flash memories referred to are a low production cost, excellent reliability (especially at high temperature), reliable electrical consumption, or high programming speed, these features being a function of the application for which they are intended.
The majority of Flash memories comprise a MOS transistor type structure (gate, source, drain and channel) comprising an electrical charge storage site, called a floating gate, formed for example by a polysilicon layer disposed between two oxide layers, and disposed between the electrically conductive gate material and the transistor channel. Storage is performed by applying to the conductive material a voltage higher than the threshold voltage, for example between 15 V and 20 V, which permits information to be stored in the form of charges trapped in the floating gate.
However, such memories have drawbacks limiting a reduction in their dimensions. A reduction in the thickness of the tunnel oxide (oxide disposed between the channel and the polysilicon layer) leads to an increase in the SILC (<<Stress Induced Leakage Current>>). The prolonged use of such a memory (repetition of write—erase cycles) generates defects in the tunnel oxide, which assist the conduction of charges and adversely affect the retention of charges in the floating gate, which causes problems in the case of a large SILC. In practice, it is therefore difficult to reduce the thickness of the tunnel oxide of these memories to less than 8 nm without the SILC becoming a critical phenomenon for storage. Moreover, by reducing the dimensions of such a memory cell, the parasitic coupling between the floating gates of two adjacent cells of one and the same memory becomes considerable and can therefore adversely affect the reliability of the memory.
For these reasons, memories of the MONOS type (Metal Oxide Nitride Oxide Silicon), also referred to as NROM memories, have been proposed to replace polysilicon floating gate memories. Document U.S. Pat. No. 5,768,192 describes such memories, in which the electrical charges are stored in traps formed in a floating gate composed of nitride and disposed between two oxide layers. In such a nitride layer, the traps are insulated from one another. Thus, an electron stored in one of the traps remains physically located in this trap, which makes these memories much more <<resistant>> to defects in the tunnel oxide, and therefore less affected by an increase in the SILC. In the presence of a defect in the tunnel oxide, the storage layer, i.e. the nitride layer, loses only the electrons located in the close vicinity of the defect, the other trapped electrons not being affected by this defect. These memories therefore have a better reliability. It is thus possible to have a tunnel oxide of thickness less than approx. 8 nm, and therefore to reduce the required programming voltages. Moreover, on account of the small thickness of nitride to form the storage layer, the coupling between two adjacent memory cells is greatly reduced compared with polysilicon floating gate cells. Finally, the structure of an NROM type memory is also suitable for producing embedded memories on account of the simplicity of the process of integration of these memories.
The document by S. Kianian et al., <<A novel 3 volts-only, small sector erase, high density flash E2PROM>> (Technical Digest of VLSI Technology, 1994, p. 71) describes another type of memory, called a <<split-gate>> memory, which comprises inside one and the same memory cell a memory transistor and a selection transistor (or control transistor) formed on a single active zone. Such a double-gate memory cell is generally programmed by the injection of carriers via the source (<<source side injection>> in English), a mechanism which precisely requires the presence of a selection transistor alongside the memory transistor, and which permits the programming speed to be increased, while at the same time reducing the consumption compared to the NROM type memory.
In order to benefit from the advantages of each structure, split-gate and NROM, document US2004/207025A1 proposes another type of double-gate memory combining the structure of an NROM type memory with a split-gate architecture. One of the difficulties in producing these memories relates to the control of the position of the gates (control transistor gate and memory transistor gate) with respect to one another.
These gates are produced by two successive photolithographies, the misalignment of the second gate with respect to the first gate fixing the length of the second gate. Poor control of the relative positions of the two gates is thus reflected in poor control of the electrical characteristics of the second transistor, and therefore potentially poor performance of the memory. Consequently, a very precise control of the position of the gates is necessary during the production of this type of memory.
In order to overcome this alignment constraint, document U.S. Pat. No. 7,130,223B2 proposes to produce a double-gate memory combining a structure of an NROM type memory with a split-gate architecture and wherein the memory transistor gate, i.e. the gate comprising the data storage layer, is produced in the form of a lateral spacer of the control transistor gate, disposed against one of the two lateral flanks of the control transistor gate. Such a structure makes it possible to control precisely the position and the size of the memory transistor gate compared with the control transistor gate because, on account of the fact that the memory transistor gate is produced in the form of a lateral spacer, the latter is therefore self-aligned with respect to the control transistor gate.
Such a structure is illustrated by FIG. 1 which represents diagrammatically a double-gate memory 1 combining the structure of an NROM type memory with a split-gate architecture, wherein the memory transistor gate is produced in the form of a lateral spacer of the control transistor gate. Memory 1 comprises an active channel zone 2 produced in a semiconductor material and comprising a channel 3 disposed between a drain extension region 4 and a source extension region 5. Memory 1 further comprises a selection transistor gate 6 surmounting a first part 31 of channel 3 and a lateral spacer 7 disposed against the lateral flank of selection transistor gate 6.
This lateral spacer 7 forms the gate of memory transistor 9 surmounting second part 32 of channel 3. This memory transistor 9 comprises in particular:                an oxide-nitride-oxide dielectric tri-layer stack (so-called ONO stack) 10, the nitride layer being used to store the electrical charges;        a conductive zone 11 of the polysilicon memory transistor gate having an essentially rounded lateral face 15;        thin spacer layers located on the rounded part of conductive zone 11, for example of high thermal oxide HTO (layer 13) and of nitride Si3N4 (layer 12). These thin spacer layers are again found on the opposite part of the selection transistor.        
Lateral spacer 7 makes it possible to insulate selection transistor gate 6 from the drain zones, but also to form memory transistor gate 9 via ONO stack 10.
However, with such a structure, it is very difficult then to produce electrical contacting on memory transistor gate 9, bearing in mind the small dimensions of this gate in the form of a lateral spacer. This contacting is for example illustrated by silicidation zone 14 located at the top of rounded lateral flank 15. It will be noted that the zone permitting the silicidation is relatively small. This difficulty is made worse by the fact that the flanks obtained by the standard processes tend to be of a triangular shape; it is in fact very difficult to obtain, by direct etching, a rounded shape permitting a sufficient silicidation surface to be obtained. One such architecture 16 is illustrated in FIG. 2. Memory 16 is identical to memory 1, but has a conductive zone 17 of triangular shape, on which silicidation zone 18 has an even more limited zone than in the case of FIG. 1.
Moreover, the article <<Scalability of split-gate charge memories down to 20 nm for low-power embedded memories>> (Masoero et al.—Electron Devices Meeting (IEDM)—2011) has demonstrated that the reduction in the length of memory gate LMG (i.e. the length of conductive zone 17 of the memory transistor gate closest to channel 3 and measured along the length of channel 3—see FIG. 1) makes it possible to improve the electrical performance of the memory, such as the programming window or the consumed energy. It can easily be seen that such a reduction in the length of the gate makes the creation of a large contact zone on the gate of the memory transistor even more difficult.